3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron

Glen Hawk, Vice President of the NAND Solutions Group at Micron, was giving the usual polished corporate keynote presentation at this week’s Flash Memory Summit held in Santa Clara, CA. Suddenly, his level tone of voice changed and he got charged up. The reason was that he was about to launch into a description of the early results of Micron’s research on 3D NAND cell technology and it was clear from his changed tone that he’s pretty jazzed about the technology. “We’ve been trapped in flatland” said Hawk. It’s time to think vertically. Geometry shrinks are slowing down and its getting harder and harder to shift to the next process node with each jump. The answer, said Hawk, is 3D NAND. We need to break through into another dimension.

Process shrinks and the associated rising complexity of manufacture are not the only reasons to make a radical change, said Hawk. There’s perhaps an even bigger problem. At 20nm, he said, we’re storing the state of a cell using approximately 20 electrons. Every electron counts in this situation and it’s easy to see why NAND Flash retention times are eroding with each shrink. Lose 10 electrons in a 20nm NAND cell and you’ve lost a lot of signal/noise ratio.

The alternative that Micron is developing is a 3D NAND Flash cell stack, shown as an illustration on the right. With this structure, each electron “trap site” is an annular ring surrounding a select line. That trap site stores 10,000 electrons, which gets NAND technology back to a safe area where there’s plenty of signal/noise margin and where retention time can go back to where it’s been. It’s analogous to the reprieve the semiconductor industry has gotten by switching semiconductor manufacture to high-K metal gate (HKMG) processing, which restored gate oxides to a realistic thickness after they’d gotten down to five or seven atomic layers—something far to delicate for mass manufacturing.

The Micron 3D NAND technology leverages a DRAM technique that Micron is quite familiar with: deep trenches. Micron and other vendors use deep trenches to build storage capacitors for DRAM memory cells. Used in 3D NAND technology, these trenches act as silos that contain NAND Flash cell stacks.

Hawk didn’t just have a nice cartoon to show the audience of 800 people attending the Flash Memory Summit. He had a microphotograph of a 3D NAND Flash memory array. Here it is:

But don’t be looking for 3D NAND Flash chips tomorrow. Hawk claimed that Micron was two years away from production of 3D NAND Flash devices.

For more analysis of presentations at the Flash Memory Summit, see this new blog entry by Richard Goering: “Flash Memory Summit: New Insights Into the Future of NAND Flash


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization and tagged , , , . Bookmark the permalink.

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