Free White Paper available on 20nm design

A number of manufacturing issues specific to 20nm pose a challenge to developing high-quality silicon and SoCs on time and on budget. Silicon Realization at such an advanced node requires a holistic approach consisting of three critical and interrelated components: unified design intent, higher levels of design abstraction, and design convergence at each stage of the flow. This approach, coupled with new lithography techniques and in-design DFM technologies, provides the most practical and predictable path to 20nm silicon.

If you need to be on the cutting edge of Silicon Realization to be competitive, here’s a brand new, just-finished-today White Paper to introduce you to some of the issues surrounding 20nm design and with some answers to the questions of how to deal with these issues:

http://www.cadence.com/cadence/Pages/downloads.aspx?cid=2

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization and tagged . Bookmark the permalink.

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