Ann Steffora Mutschler’s interview with Scott Graham, general manager for Micron’s Hybrid Memory Cube (HMC) and Joe Jeddeloh, whose team developed the logic portion of the HMC alerted me to the existence of Micron’s new Hybrid Memory Cube, a 3D assembly of DRAM chips plus logic that creates a compact, high-speed DRAM component that significantly reduces the power required for DRAM access. Here’s a small image of the planned component:
The HMC is a stack of multiple memory die sitting atop a logic chip and a substrate, all bonded together using TSV (through silicon via) technology. The objective of this approach is many fold. First, this approach greatly increases available DRAM bandwidth by leveraging the large number of I/O pins available through TSVs. How much faster? The claim is that the HMC delivers 20x the bandwidth of a DDR3 memory module.
Next, the die stacking significantly reduces the amount of volume needed to hold a significant amount of DRAM. How much smaller? The HMC requires about 10% of the volume of a DDR3 memory module.
Finally, the HMC draws less power because it the wider I/O capabilities and greater I/O bandwidth significantly cut the amount f energy needed per bit? How much less? The HMC requires about 10% of the energy per bit of a DDR3 memory module.
Here’s an image from Micron that illustrates all of these attributes:
This short, well-done video from Micron provides some additional, tantalizing details.
Now you can’t rush out and buy these Hybrid Memory cubes today. The company is saying that it plans to be in production during the second half of 2013.
See also: 3D Thursday: Power is a killer app for TI’s PowerStack 3D packaging—parasitics vanish
and Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
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