Although DDR3 memory is just ramping up in sales, JEDEC has been working on the next-generation DDR4 specification for faster SDRAM that consumes even less power. To achieve these goals, JEDEC announced yesterday that has specified the following key features in the DDR4 spec:
- Maximum initial per-pin transfer rate of 1.6 Gtransfers/sec (with possible increase to 3.2 Gtransfers/sec in the future)
- DQ bus terminated to 1.2V VDDQ (allowing possible future voltage reduction in VDD to save power)
- Pseudo open-drain I/O on the DQ bus
- Three data widths: x4, x8, x16
- 8n prefetch with 2 or 4 bank groups
- Bank group architecture with separate activation, read, write, refresh operations for each bank group
- Geardown mode for DDR4-2667 and beyond
- Internally generated VrefDQ
- Improved training modes
- Differential signaling for clock and strobes
- Dynamic on-die termination
- CRC for the data bus for non-ECC memory applications
- CA parity for command/address bus
- DLL-off mode for power savings
Publication of the full standard is expected in mid 2012 and JEDEC is planning to host a DDR4 Technical Workshop after the standard is published.
Just as a reminder, Cadence announced a DDR4 IP solution back in April that includes hard and soft PHY IP; controller IP; memory models; verification IP; tools and methodologies; and signal integrity reference designs for the package and board. Although the specification is still a year off, early SoC designs using the DDR4 SDRAM interface specification need to start now to be ready to catch the first wave when DDR4 memory modules start to appear.
Also, see “The DDR4 SDRAM spec and SoC design. What do we know now?” published earlier in the EDA360 Insider.
EDA360 Insider 
And yet the recently leaked slides on the Haswell microarchitecture indicate support only for variants of DDR3…is Intel refusing to back DDR4 or holding off until a later (2014+) architecture?