What do you need to know about IP for SoC Realization?

Ron Collett, the IC industry’s most experienced ASIC and SoC project actuary—CEO of Numetrics and the man who first recognized and named the “Design Productivity Gap” —has just published an interesting essay on IP reuse in EETimes titled “The realities of IP reuse”. Collett writes: “…most IC development teams fail to recognize a critical non-linear relationship exists between the amount of circuitry they modify or ‘improve’ in pre-existing IP blocks and the effort the engineering team expends in making those modified blocks operate properly in the target IC.” Here, Collett is writing about development teams modifying IP, often internal IP, for a new application. Later in the essay, Collet says “It’s an insidious problem that often disrupts the entire project development pipeline, as resources fail to roll in a timely manner from one project to the next.”

These issues also connect to the problems with using commercial IP. Just as with any product category, there are varying quality levels for commercial IP. A lot of commercial IP has not been fully productized, meaning that the IP lacks one or more of the following: thorough verification and debugging, complete documentation, scripts required to include the IP in an SoC design, associated verification IP, and an ongoing support strategy. Oh yes, the IP had better be silicon-proven as well. Often, internally generated IP lacks most or all of these. As SoCs increasingly depend on existing and third-party commercial IP, these are issues to keep well in mind.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, SoC Realization. Bookmark the permalink.

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