3D Thursday: The elephant that’s 3D—Musings about 3D chip assembly on LinkedIn

Sometimes, the group discussion threads on LinkedIn become showcases for the varied opinions of the members. Such was the case when Elena Neira, Director of Technology at Verizon Wireless, asked “Is Moore’s Law still pacing the Semi Industry?” in the Semiconductor Professionals Group. Here are some 3D-related comments posted in response to Neira’s question that I found interesting:

  • Planar CMOS has probably hit a limit. Clock-rates across-chip and on-and-off-chip are at a wall (~3 GHz) until you go optical. There is nanoelectronics and 3D that will probably offer a way out on the bottom end. For photolithography, sub-wavelength resolution plasmonic lithography might do the job of patterning smaller.—Jeff Gruszynski, Director of R&D, Core Wafer Systems
  • Now that monolithic 3D is practical (see MonolithIC 3D web site) there is clear path for Moore’s Law to continue on for at least the next two decades. There is a big difference between TSV type 3D IC and what I am talking about – monolithic 3D (10,000x vertical connectivity)! With monolithic 3D IC every folding is equivalent for 1 node of scaling from every point one look at. —Zvi Or-Bach, President & CEO at MonolithIC 3D Inc.
  • I don’t see anything like a 20-year extension from 3D alone – but it may buy about 1.5 generations overall…I’m sure that monolithic 3D techniques have a role to play; but, equally, I believe that we need to be careful not to undermine its credibility by apparently overselling the potential.—Hedley Rokos, Adaptalog Limited

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization. Bookmark the permalink.

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