At the final presentation I attended at last week’s Global Technology Forum, Manoj Chacko from Cadence discussed how to get “everything you’re entitled to” with In-Design DFM (Design for Manufacturing). Two of the key yield detractors Chacko discussed are yield losses due to CMP (chemical mechanical polishing) and LDE (layout dependent effects). CMP is an abrasive manufacturing step used to re-planarize the top of a silicon wafer to prepare it for the next layer and it’s a key process that enabled the use of multiple copper interconnect layers. During CMP, a thick additive copper layer erodes away until only the desired interconnect wires—set into trenches in an insulating layer—remains. This is the so-called Damascene process named for the intricate metal inlay work and the patterns that appear on swords made famous in ancient Damascus. Unfortunately, CMP can cause a number of problems that result in yield loss. Here’s a graphic showing these problems:
All of the losses result from accidentally removing too much material from the wafer. Copper is a soft metal and it’s easily removed. It turns out that certain metal patterns are more susceptible to overpolishing than others so it’s important to have a way of identifying hotspots—patterns known to be a problem—so that they can be identified and so that the layout can be fixed before actually manufacturing the wafers.
Similarly, there are a range of known LDE problems and these too are layout-sensitive. Here is a list of LDE problems.
As you can see, there are several different LDE problems that can cause transistor parametric variation depending on context, placement, and density. However, the thing to take from the above chart of LDE yield detractors is that few of them were a problem before the 40nm node; all of the effects listed became problems at the 40nm node; and more of the effects became bigger problems at the 28nm node (as shown by the big red “X”s).
The result, Chacko said, is that at 40nm , there were only few CMP and LDE yield problems so they could be addressed and fixed manually. At the 28nm node, a chip design might see 10 to 100 hot spots—still few enough to fix manually but starting to be a real headache for Silicon Realization teams. At 20nm and below, the only sane way to address these yield detractors is with automation and in-design checking. There’s simply not enough time in a development cycle to catch these problems late in the design flow and then iterate on the design.
To automate this process, you need two things. First, CMP and LDE in-design pattern checking must be built into the EDA tools. Cadence has done this for its Encounter (digital) and Virtuoso (custom/analog) EDA tools by building DFM engines into the tools. Second, you need a set of known problem patterns to check against. Cadence has worked with GLOBALFOUNDRIES’ process engineers to develop these patterns for various process nodes.
“GLOBALFOUNDRIES has a rigorous approach to developing these patterns” said Chacko. “There are thousands to check against.” Silicon Realization teams simply cannot do this checking manually. There are potentially hundreds of problems on each unchecked IC design and thousands of patterns to check against. You need automatic matching and fixing to tackle a problem of this magnitude. The result of adding this automated checking and fixing to the design flow, said Chacko, is in-design pattern checking and repair that’s 100x to 400x faster than litho signoff because in-design checking and fixing eliminates time-stealing iterations through the design flow to mitigate these problems.