How can you be sure DDR2, DDR3, and DDR4 SDRAMs will work properly in your system?

LeCroy introduced an upgrade to its Kibra 380 DDR3 SDRAM protocol analyzer today. The analyzer’s probes plug in series with the DDR3 SDRAM modules and the analyzer can identify more than 65 JEDEC command protocol and timing violations in real time. This kind of hardware verification capability is critical, once you have the hardware in hand to test. However, it’s also critical to verify DDR3 (plus DDR2 and DDR4) protocol and timing long before the board is built and even before the SoC containing the DDR controller is fabricated. To do that, you need the appropriate DDR verification IP (VIP) such as the Cadence Incisive Verification IP for DDR protocols.

Verification IP is especially important for finding problems in complex interconnect protocols and the protocols for managing DDR SDRAMs gets a bit more complex with each generation. These memories are far, far different than the old asynchronous DRAMs of the 1990s. They’re full of little state machines that operate the multiple DRAM banks within the memory parts. Violate the appropriate DDR protocols and you might well end up with lost data. The Cadence VIP for DDR memory now performs more than 140 automated protocol checks to ensure proper controller behavior under all conditions by automating stimulus generation and result checking and by supporting metric-driven verification.

Coincidentally, Cadence is demonstrating this VIP starting tomorrow at the Intel Developer Forum being held at the Moscone Center in San Francisco, CA.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization, Verification and tagged , , , , . Bookmark the permalink.

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