One week ago, I described some of the 20nm process node benefits and challenges discussed in Wei Lii Tan’s presentation at the recent Global Technology Conference. (See “Just how high is the 20nm design mountain of challenges?”) Now Richard Goering has covered the topic of 20nm design in more detail with his interview of Cadence product marketing director Rahul Deokar. Here are some of the high points from that interview:
- There are three primary reasons to migrate to 20nm: performance (approximately 50% better than 28nm), lower power (about 30% savings in switching power), and transistor density (8 to 12 billion transistors per chip).
- Metal-pitch shrinkage at 20nm causes increased wire coupling, which amplifies the on-chip variability problem and makes device modeling more complex. Layout-dependent effects mean that placement and routing become much more complex at 20nm.
- Double patterning is required at 20nm for perhaps the bottom five metal layers to accommodate the desired wire pitch. Above layer 5, you might not need double patterning because geometries get larger as you move up the metal stack. Through double patterning, 193nm optical lithography dodges yet another bullet. “Double patterning has to be integrated inside of the routing solution” and silicon IP must be designed to comply with double-patterning layout rules. You cannot decompose a single-pattern design into a successful double-pattern design. Cadence tools in the 20nm Silicon Realization flow implement an automatic, colorized placement and routing for double-patterned designs that’s correct by construction.
- SoC complexity is a growing problem (remember 8 to 12 billion on-chip transistors!) so Cadence has developed an automatic abstraction technique called Flex Models that abstracts portions of large SoC designs into design macros or blocks to reduce the complexity. This approach helps drive faster design convergence.
- The Azuro clock-concurrent optimization technology (CCOPT) that Cadence recently acquired generates significantly better power, performance, and area results for the complex clock networks you find in 20nm SoC designs. (See “Wondering why Cadence bought Azuro? Here is Richard Goering’s analysis of the acquisition and “Clock Concurrent Optimization” and “Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?”)
- 20nm SoC design is here today. Cadence is working with partners on several test-chip tapeouts.
(For the full interview, see “Q&A: A Look at 20nm Design Challenges and Solutions”)