3D Thursday: Design 3D die stacks with test in mind

You can read an excellent new article on test challenges for 3D IC design here. The article was written by Samta Bansal of Cadence and Herb Reiter, Chair of the GSA’s 3D-IC working Group. The article discusses the key differences between wire-bonded SIP (systems in package) 3D IC stacks and 3D IC stacks based on TSV (through silicon via) interconnects. There are orders of magnitude more interconnects when using TSVs and that means that the testing challenges grow accordingly.

One issue covered in the article is “Who tests what and when?” There are individual die, partial assemblies and complete 3D assemblies that might be tested. Many considerations must be considered before deciding on what to test and when. You don’t want to retest already tested components unless absolutely necessary because doing that just adds cost, not value.

Another significant consideration is the matter of probing 3D assemblies. As the article states, “Current probe technology cannot access TSVs or micro-bumps.” One future solution is finer probes but until then, dedicated test pads that can be probed are required to provide tester access. What are the chances that such probe points already exist on a schematic somewhere?

The article concludes with a discussion of test standards. Imec and Cadence have been working together to develop 3D IC test standards because without them, the problems will only become worse. See “DFT for 3D-IC: It’s déjà vu all over again” for more information on that topic.

And be sure to read the new article.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Packaging, Silicon Realization, SoC Realization, System Realization. Bookmark the permalink.

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