Last Thursday, I wrote a blog entry on the agreement between IBM and 3M to develop advanced adhesives to aid in 3D die-stack assembly and heat removal. (See “3D Thursday: Can IBM and 3M really build a 3D, 100-chip stairway to heaven with glue?”) The announcement spurred some interesting feedback from members of the LinkedIn Semiconductor Professionals Group.
Henry Burbank wrote: “About 20 years ago at IBM I was involved in a research project to make Silicon on Silicon products, similar to the 3D technology. I was a processor test manager and was responsible for developing and implementing an overall test strategy. The issue boiled down to test coverage and rework. If the devices had low test coverage the rework costs became the main issue. At that time, It is very difficult to rework glass. The 3D stacking technology will need some type of self correcting method of rerouting any nets on the stacked devices that may fail over time. The stacking of die can be a great way to increase inter-chip speeds and functionality. It will be expensive if the sandwiched devices have less than 99.999% test coverage and the overall reliability could be impacted, causing an increase in failure rate. There are some thermal coefficient matching and mechanical advantages to silicon on silicon.”
To which Tryggve Mathiesen replied: “So based upon your message Henry, 100% tested chips with potential selfcorrection methods, as well as upgradable with correted functionality after fault detection.
It sounds like 3D stack of FPGA and Memory devices to me!
But we still have the power issue, micro/nano heatpipe technology?
Other solutions, like the 2.5D solution from Xilinx SSI making a “flat” stacking on an interposer – overcoming the size/IO limitations, but only true 3D will give you “unlimited” integration area.
Looking forward to follow this discussion”
I then added this: “Henry, I agree with you that rework considerations are currently thorny. As we did with surface-mount boards, there’s a cold equation with respect to what gets fixed and what gets tossed for 3D, but we don’t yet know the parameters. Surface-mount technology was also the spur for JTAG testing. I recall when there were many JTAG doubters and detractors. “We cannot afford to devote 2% or 4% of our chip to test structures” was the cry. Now, no one thinks twice about this. I predict the same will happen for built-in-test once people start to realize that SoCs contain so many on-chip processors that could be used for on-chip functional and power-up testing. Why not? We just need a test methodology that can harness these heterogeneous processor collections.
Tryggve, I agree with you that 3D gives more integration ability than 2.5D interposer technology. I also realize that the interposer technology is simpler and may be a very effective way to get “enough” integration area. It does for Xilinx. I know that even interposer technology presents some interesting technical challenges to be worked through, as does any technology when new. Somehow, it’s never as simple as falling off a log, as they say. Cooling is an issue to be dealt with no matter what semiconductor and packaging technologies you use.”
And finally, Charles J. Vath, III contributed this: “Papers have been presented on the thermal issues in 3D stacked modules. It begins to look like a Rubik’s Cube problem. Moving parts of the various chips around in three dimensions can help alleviate the hot spots. Perhaps on chip, sub-test circuits could validate intra-stack as well as inter-stack performance.”
What do you think?
EDA360 Insider 