What’s it take to design DDR4 into your next SoC? Newly released DFI 3.0 Spec opens the flood gates for DDR4 design

DDR4 SDRAM probably won’t be appearing until 2013 and probably won’t become the mainstream SDRAM technology until 2015 (updated estimates from “Memory to processors: “Without me, you’re nothing.” DDR4 is on the way.”) but the new DFI 3.0 preliminary specification from the DDR PHY Interface (DFI) Technical Group goes a long way towards making it possible for ASIC and SoC chips to incorporate DDR4 memory interfaces into their design now so that they’re ready for the future. The DFI specification defines a standard interface between a memory controller (MC) and a memory PHY and the DFI Technical Group includes representatives from ARM, Cadence, Intel, LSI, Samsung, ST-Ericsson, and Synopsys so you know there’s some weight behind this specification. By defining this standard interface, the DFI spec permits independent development of DDR MCs and PHYs, shown below, which gives SoC and Silicon Realization teams more choice.

The existing DFI spec needed updating to accommodate the new DDR4 features and the DFI 3.0 specification incorporates those updates.

There are six key categories for the DDR4 updates to the DFI spec:

  1. Addition of support for DDR4 CRC (cyclic redundancy checks)
  2. Addition of command and address parity signaling
  3. Support for CRC and parity errors
  4. Support for data bus inversion (DBI)
  5. DDR4 DQ training support
  6. Addition of new command signals and parameters

You can download the new DFI 3.0 preliminary specification here.

Note: Cadence has simultaneously announced that its DDR SDRAM controller IP, DDR PHY IP, and DDR4 verification IP now all support the DFI 3.0 specification.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Memory, Silicon Realization, SoC Realization and tagged , , . Bookmark the permalink.

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