Processor Wars: NVIDIA reveals a phantom fifth ARM Cortex-A9 processor core in Kal-El mobile processor IC. Guess why it’s there?

NVIDIA has extended the path to many-core design by publishing a White Paper that reveals the existence of a fifth ARM Cortex-A9 processor core in the company’s previously discussed Kal-El mobile processor. This fifth processor core implements what the company is calling “variable symmetric multiprocessing” (vSMP) and it’s purpose is to provide extremely low-power operation during periods when the end product in an active standby mode—when it’s performing background tasks such as email and social media synchronization or running active widgets. As the NVIDIA White Paper states “Users generally do not care how fast the background tasks are processed, only that they happen and do not consume much battery life.”

The fifth core’s advantage arises from it’s differentiation from the other four ARM Cortex-A9 cores. The four main cores are optimized for performance using fast transistors. These transistors leak more, so these four processor cores dissipate relatively more static power. The fifth ARM Cortex-A9 processor core, the one NVIDIA calls the “Companion” core, uses the same architecture but it’s been designed with transistors from the foundry’s low-power process. Consequently, the Companion core cannot achieve the same high clock rates, but it consumes less power at low frequencies compared to the other four on-chip processor cores.

The Kal-El mobile processor chip is designed to allow independent control of all five processor cores. In practice, when the Companion core is running, the other four high-speed cores are not. When one or more of the high-performance processor cores is operating, the companion core is not. This rule permits easier software switching from the low-power core to the fast cores and produces a power curve that looks like this:

The green part of the curve represents the operation domain of the Companion processor while the red part of the curve represents the operation domain of the four other ARM Cortex-A9 processor cores.

Workload management is performed by NVIDIA’s dynamic voltage and frequency scaling (DVFS) and CPU Hot-Plug management software. No other OS modifications are needed to make this scheme work.

Here’s a graphic from the NVIDIA White Paper that gives you an idea of how the processors are switched on and off for given load classes:

The resulting power savings are fairly impressive:

  • MP3 playback: 14% power savings
  • HD video playback: 61% power savings
  • Gaming: 34% power savings

NVIDIA’s approach to adding a fifth processor core as a means to lowering power consumption in a multi-mode operational environment may seem radical but it is something clearly on the path that Moore’s Law is taking in the nanometer era. Ever since Dennard Scaling broke at the 90nm node, Moore’s Law transistor density increases have not been accompanied by corresponding increases in transistor speed or in the amount of power reduction with each process step as we’d become accustomed to seeing for several decades. Therefore, Silicon Realization design styles that are based on the assumption that Moore’s Law and Dennard Scaling were in lockstep have increasingly been diverging from reality for several years. NVIDIA’s vSMP design approach explicitly takes advantage of a newer design approach that exploits the additional transistors to create a device that runs well under both high and low workloads.

The NVIDIA Kal-El mobile processor is an excellent example of design driven by all of the EDA360 Realizations: System, SoC, and Silicon. It is a design style that fits the reality of 21st-century SoC development.

A tip of the hat to Dean Takahashi for his article on this topic, which appeared today on


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in Android, ARM, EDA360, Honeycomb, IP, Low Power, Silicon Realization, SoC Realization, System Realization and tagged , , , , . Bookmark the permalink.

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