3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors

One more process node click, from 45nm to 32nm, bumped the clock rate of the Ambarella A7L SoC’s on-chip ARM 1136J-S RISC processor core to 600MHz from 528MHz. But reading the press release, I get the impression that the real reason for jumping to 32nm was for lower power. Because the A7L SoC is aimed at digital still cameras (DSCs), power consumption is critical because it directly translates into numbers that consumers really care about: shots per battery charge and minutes of recorded video per battery charge. Aiding in that power minimization is the division of image and video encoding and decoding into separate DSPs, each optimized for  the task. And that is the real value of low-power operation, isn’t it? It’s to make the end product more attractive, more valuable, or perform better than competitive products.

The following block diagram clarifies the A7L SoC architecture:

The A7L SoC’s block diagram illustrates the three processor cores that sit at the heart of this device. A host of camera-specific peripherals surrounds this 3-processor complex. To aid in the reduction of BOM cost and power consumption, the A7L SoC can capture full 1080p HD video at 60 fps, capture 16-Mpixel RAW images at 30 fps, or capture full HD video and Mpixel still images simulataneously—all with just one 16-bit-wide DDR3 SDRAM.

All of this on-chip processing power allows the A7L SoC to perform some fairly advanced image processing in real time. Here are some examples:

  • Advanced image stabilization for both recorded video and still images
  • Real-time, geometric distortion filtering to get better images from inexpensive zoom lenses
  • Multi-frame high-ISO and HDR (high dynamic range) image acquisition

These are the kind of cutting-edge features that will attract advanced camera purchasers to a new camera design.

Ambarella has also created a hardware development platform that includes tools, software, and a hardware reference design with schematics, a BOM, and a board layout. Here’s a photo of the A7L hardware platform:

This inclusion of software and development tools illustrates the complete offering that semiconductor vendors must offer with SoCs of this complexity.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, Firmware, Low Power, Memory, Silicon Realization, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

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