For years, SoC Realization teams have used FPGA prototypes as an essential part of the design-verification process. Creating one-off FPGA prototypes is hard however, and it distracts the team from the real goal—designing the SoC.
It does not need to be that hard. You can find out how.
If you want to know more, there are two ways to sign up for a free seminar on state-of-the-art Soc prototyping. You can go to a live session or you can watch an online Webinar.
Live North American sessions are scheduled for:
- Tues, Oct 25, 2011, 1:00 – 4:15pm, Irvine
- Thurs, Oct 27, 2011, 1:00 – 4:15pm, Austin
- Tues, Nov 8, 2011, 1:00 – 4:15pm, Chelmsford
- Thurs, Nov 10, 2011, 1:00 – 4:15pm, Ottawa
- Tues, Nov 15, 2011, 1:00 – 4:15pm, San Jose
If that’s not conventient, there are a series of related System Realization seminars just about to start in the EMEA region:
- 04 Oct 2011 – Grenoble, France (Novotel Grenoble Centre)
- 06 Oct 2011 – Munich, Germany (Cadence Office)
- 11 Oct 2011 – Eindhoven, The Netherlands (High Tech Campus)
- 13 Oct 2011 – Bracknell, UK (Cadence Office)
- 07 Nov 2011 – Herzelia, Israel (Cadence Office)
You can sign up for one of the live North American seminars here: http://j.mp/n2lhns
Sign up for one of the EMEA System Realization seminars here: http://j.mp/rpcMLC
And you can watch the online Webinar here: http://j.mp/oENaYg