How would you like some of Cisco’s SoC implementation secrets? Get them at this ARM TechCon session

You know that doing a hasty or inadequate job at the SoC architectural level will cost you in the implementation schedule. If only you could get a few good tips on how to beef up that architectural design-space exploration. Well, you can on October 25 during the chip-design day at ARM TechCon 2011, being held at the Santa Clara Convention Center. Cisco and Cadence are giving a joint presentation on how Cisco performs early SoC implementation analysis and design-space exploration with a range of architectures, IP choices, and IP integration strategies to shorten the implementation phase and boost chip manufacturability. This is a rare chance to look over the shoulder of a successful design team and glean what tips you may.

Read more about the session here:

Early Architectural Planning for Increased Productivity, Predictability and Profitability

Sign up here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , . Bookmark the permalink.

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