Master the secrets of system design using DDR4 SDRAM

It is rare that you get to sit at the feet of a certified master and learn. If you’re interested in designing with DDR4 SDRAM, then this is your chance. On Tuesday, October 25, at ARM TechCon, Marc Greenberg will discuss the complex relationship between DDR4 memory, large SoCs, memory latency, and system performance. Greenberg is a certified master. He spent years at Denali Software absorbing everything a design team needs to know about using memory in systems. Now he’s Director of Product Marketing for the DRAM Design IP products at Cadence and I’ve heard him speak several times. Long before I joined Cadence. He is truly a master on memory topics.

Read more about his presentation here:

DDR4, Higher Speeds, and Larger SoCs: Why External Memory Latency is Getting Worse, and What to do About It

Sign up here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Memory, SoC Realization, System Realization and tagged , . Bookmark the permalink.

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