Want some more details about the Samsung 20nm test chip? Here’s your chance: ARM TechCon 2011 on October 25

Later this month, you have the opportunity of attending the ARM TechCon 2011 conference being held in the Santa Clara Convention Center in California. Tuesday, October 25 is dedicated the many different aspects of advanced to SoC design and the following two days, October 26-27, are dedicated to software and systems design. One Tuesday session you might find very interesting is titled “ARM nSTEP Microcontroller Implementation Using Cadence Silicon Realization Flows in Samsung 20nm Technology” being given jointly by speakers from ARM, Cadence, and Samsung. This case-study session discusses experience gained in the development of the ARM Redcliff test chip targeting the Samsung 20nm process technology. The test chip included two on-chip ARM nSTEP microcontrollers based on an ARM Cortex processor core. Each of the two microcontrollers was optimized differently using Cadence tools to exercise the Samsung process technology. The tool set included static and dynamic power signoff; functional verification; scan/ATPG; multi-mode, multi-corner (MMMC) timing signoff; full-chip LVS/DRC check; and the Cadence NanoRoute router.

For more information about the Samsung 20nm test chip, see this previous EDA360 Insider blog entry from July.

Sign up for ARM TechCon 2011 here. It’s coming sooner than you think.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 20nm, ARM, EDA360, Samsung, Silicon Realization, SoC Realization and tagged , , , . Bookmark the permalink.

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