Want a shortcut to automating assertion generation for simulation, formal verification, and emulation flows?

Assertion-based verification (ABV) helps ASIC and SoC design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that define the intended behavior of signals in the design. “Assertion synthesis” promotes ABV proliferation by automating the often painful, very manual process of creating meaningful white-box assertions and functional coverage properties with sufficient capacity to handle today’s immense and complex SoC designs.

If this sounds good to you and you want to know where to begin, there’s a free 1-hour Webinar next week that can start you on this path. It takes place on October 13 at 9 am Pacific Time. Sign up here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, System Realization, Verification and tagged , . Bookmark the permalink.

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