Still baffled by “in-design” DFM signoff for SoC and Silicon Realization? Read this

Richard Goering has just published a detailed analysis of “in-design” DFM signoff and how it can accelerate chip implementation. Heck, it can prevent the usual fire drill that occurs just before tapeout; Instead of facing more than 100 problems that need to be fixed immediately, instead of holding up tapeout until the fire drill can be finished, why not just take the relatively small amount of time needed to find and fix layout problems as they occur at the block level? If you do that, your problems at tapeout will likely be greatly reduced.

Read here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in DFM, EDA360, Silicon Realization, SoC, SoC Realization. Bookmark the permalink.

One Response to Still baffled by “in-design” DFM signoff for SoC and Silicon Realization? Read this

  1. George Storm says:

    What??
    I have never worked anywhere that cell or subsystem sign-off was not an absolute requirement before incorporation at a higher level.
    Issues can still arise, of course

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