It’s been more than a year and a half since Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq. It seemed inevitable that Altera would eventually counter with a competing product line and it did. Today, Altera revealed plans for a line of chips called SoC FPGAs.
The Altera SoC FPGA line will include an extensive array of different chips with various configurations for the on-chip “Hard Processor System” (HPS) and various size on-chip FPGA fabrics connected to the HPS block. The SoC FPGA product line will be based on two of the Altera 28nm FPGA fabrics—Cyclone V and Arria V—for two different speed grades within the SoC FPGA product line. Here’s a generalized block diagram of a device in the product line:
The SoC FPGAs’ HPS is based on two 800MHz ARM Cortex-A9 processor cores with ARM Neon and single/double-precision FPU extensions. Each ARM Cortex-A9 processor has its own L1 caches—separate 32Kbyte L1 caches for instructions and data. The two processor cores share a unified 512Kbyte L2 cache. Each processor also has private interval and watchdog timers. To keep the two processor cores fed with instructions and data, there’s a hard-core, multiport DDR SDRAM controller in the HPS that supports DDR2 and DDR3 and LPDDR1 and LPDDR2 SDRAM interface protocols. There’s also a Flash memory controller with a built-in DMA engine. The NAND Flash controller supports NOR and NAND Flash memories including ONFi 1.0 devices and SD, SDIO, and MMC memory cards. In addition, there’s ECC support for the SDRAM and the NAND Flash interfaces.
Next up are the hard-core peripherals within the HPS. There are a lot of them:
- Two 10/100/1000 Ethernet MACs with DMA
- Two USB 2.0 On-The-Go (OTG) controllers with DMA
- Four I2C controllers
- Two CAN (Controller Area Network) controllers
- SPI Master and SPI Slave ports
- Two UARTs
- General-purpose ports
On-chip memory includes 64Kbytes of RAM and a boot ROM.
That’s already quite a lot for System Realization teams to work with, but then there’s the FPGA section of the SoC FPGA. On-chip FPGA capacity varies depending on whether the particular SoC FPGA device is based on the Cyclone V or Arria V FPGA fabrics. Devices based on the Cyclone V FPGA fabric will be offered with 25K, 40K, 85K, and 110K logic elements. Devices based on the Arria V FPGA fabric will be offered with 350K and 460K logic elements.
The HPS in the SoC FPGA connects to the on-chip FPGA though two 128-bit AXI buses—one for reads and one for writes—plus a 32-bit AHB peripheral bus for slower-speed peripheral devices. In addition, there are ports going directly from the FPGA array to the SDRAM controller in the HPS.
As you can see from the block diagram above, the hard-core peripherals not included in the HPS block separately connect to the FPGA fabric. What’s not apparent from the diagram is that the two ARM Cortex-A9 processors share a Snoop Control Unit (SCU) and there’s an ACP (accelerator coherency port) linking the HPS to the FPGA fabric so it’s possible to engineer accelerators that maintain coherency with the ARM Cortex-A9 processor cores’ caches and implement them using the on-chip FPGA fabric.
In addition to the six FPGA array sizes—four sizes for devices based on the Cyclone V FPGA fabric and two sizes for devices based on the Arria V FPGA fabric—Altera plans to offer the parts with three HPS subsystem configurations: base, mid, and high. Combined with the six FPGA fabric sizes, that means there are at least 18 Altera SoC FPGA parts planned for the initial product lineup.
Altera says that there will also be 1-processor variants in the SoC FPGA lineup. Just in case you suspect that’s perhaps a bit underpowered, keep in mind that essentially 100% of all system designs based on microcontrollers use one far less capable processor core than an 800MHz ARM Cortex-A9 core. So if you think one microprocessor just isn’t enough these days, you might want to check just to make sure you’re not becoming overly acclimatized to multicore designs. On the other hand, if you’re planning to run Android, you want the two cores.
As the block diagram above shows, there are additional hard-core peripherals connected to the SoC FPGA’s on-chip FPGA array: as many as three more multiport SDRAM controllers, a Gen2 x4 PCIe port (supplemented with the possibility of implementing an additional soft Gen2 x8 PCIe port in the FPGA fabric), as many as six 10Gbps high-speed differential serial transceivers, and as many as thirty 6Gbps high-speed differential serial transceivers. These additional peripheral ports all have separate access paths into the FPGA fabric of the SoC FPGA devices to create an appropriate amount of transfer bandwidth into and out of the FPGA fabrics.
Perhaps the most interesting news here is that low-end members of the Altera SoC FPGA family will sell “below $15” in “high volumes.” That’s a lot of capability for a relatively low price. In fact, that’s a very low price in the FPGA world. The bad news is that Altera doesn’t plan to ship these devices until the second half of 2012. Nevertheless, like the dual-core Qualcomm Snapdragon 4 SoC discussed yesterday in the EDA360 Insider, the Altera SoC FPGA family is yet another illustration of the immense System realization abilities made possible by 28nm process technology.