Experimental , ultra-low-power 1.2V, 65nm SoC from ST and MIT operates at 82.5MHz (!) maximum, 540KHz at 0.54V

Last week, ST Microelectronics and MIT’s Microsystems Technology Laboratory announced the development of a low-power 65nm SoC that operates an on-chip microprocessor core at supply voltages as low as 0.54V and the on-chip SRAM with supply voltages as low as 0.4V. The objective is to develop technology that runs on extraordinarily low power for wireless sensors and for implantable biomedical applications. A closer examination of some of the Silicon Realization team’s design choices is quite illuminating.

Here’s a block diagram of the SoC:

First, this SoC doesn’t employ a standard RISC processor core; It’s a 32-bit processor architecture unique to ST called the ReISC (Reduced Energy Instruction Set Computer) core, which relies on extensive clock gating and variable-length instructions (16, 32, or 48 bits) to help it achieve low power operation. The design target for clock rate was 82.5MHz at 1.2V and sub-1MHz at 0.6V, so this is already a very unusual design.

Because of the slow clock rates, you would think that this processor would not need instruction or data caches and you’d be right—it doesn’t need caches for performance. However, this processor does have instruction and data caches. They’re 128 bytes (not Kbytes, bytes) each. The small, latch-based caches are 128 bits wide so they serve as interfaces to the SoC’s on-chip 8Kbyte instruction and data SRAMs, which is also 128 bits wide to minimize the energy required for memory accesses. The caches are not faster than the local on-chip memories—there’s a zero-cycle miss penalty—but if there’s a cache hit, then the SoC need not run a memory cycle on the larger memory arrays, which saves energy.

The reason for this focus on saving energy in memory access cycles is because roughly 50% of the total energy consumption in embedded systems is now used to power the memory subsystem, so there’s a substantial energy savings to be had.

Like the on-chip caches, the on-chip SRAMs are also unusual. They use an 8-transistor design rather than a conventional 6-transistor SRAM cell design. The extra two transistors in the SRAM cell decouple the cell’s read ports and prevents read-disturb effects when the SRAM operates at low supply voltages. This design approach allows the SRAMs to operate with supply voltages as low as 0.4V although the write voltage for the word-line drivers must be raised to 0.6V for reliable write operations. The net effect of the split supply voltage on the SRAM array is a 23% energy savings. Clearly, there’s a tradeoff here between the extra two transistors used per cell and the resulting energy savings.

At 1.2V operating voltage and 82.5MHz, the SoC consumes 41.7pJ/cycle. At the low-voltage design target of 0.6V, the SoC runs at 1.65MHz and consumes 10.8pJ/cycle. At its lowest operating voltage (0.54V), the SoC operates at 540KHz (!) and consumes 10.2pJ/cycle.

Note: The clock rate of the Intel 4004, the world’s first commercial microprocessor introduced in 1971, was 740KHz using 10-micron (10,000nm) lithography. the Intel 4004 microprocessor executed 46,000 to 92,000 instructions/sec.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 65nm, EDA360, Low Power, Silicon Realization, SoC, SoC Realization and tagged , . Bookmark the permalink.

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