Want to know the secrets of implementing an ARM Cortex-A15 in an advanced process node? Read on!

ARM and Cadence have just announced the tape out of the industry’s first 20nm design based on the ARM Cortex-A15 MPCore processor. The test chip targets TSMC’s 20nm process and it was jointly developed by engineers from ARM, TSMC, and Cadence using a Cadence RTL-to-signoff flow. Today’s announcement is the end result of an 18-month collaboration between ARM and Cadence to develop optimized design flows specifically for the Cortex-A15 processor core.

Next week, you will have a chance to gain from the experience of engineers who have successfully taped out an SoC based on the ARM Cortex-A15. They will tell you hard-won development secrets at the cutting edge of SoC Realization. The talk covers the complete digital Silicon-Realization flow—from physical-aware logic synthesis to DFT, timing optimization, optimized CTS (clock tree synthesis), and routing.

The presenters are Bhasi Kaithamana is Implementation Manager-ARM Processors with Austin Design Center(Wireless Business Unit) at Texas Instruments and Paddy Mamtora, Product Engineering Director in IC Digital Implementation and Analysis division of Cadence.

The talk is Tuesday, October 25 from 11 am to noon at ARM TechCon 2011. More details here.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in ARM, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSMC and tagged , , , , . Bookmark the permalink.

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