Deepak Sekar, Chief Scientist of MonolithIC 3D Inc, published a blog about power distribution in 3D ICs way back in March but a recent discussion post on LinkedIn has highlighted it once again. Sekar writes about several ways to approach the problem of distributing power on 3D ICs but perhaps the last two sentences in his post is the one to read first:
“Of course, the first logic-on-logic 3D-ICs will probably consume <1W and be used for smart-phones and tablets. It should be easier to handle the power delivery problem there.”
As the power goes up, the power-distribution problems become more important. According to Sekar, 20W is the threshold and the first problem is that 3D ICs with their stacked active layers will naturally have greater power density per square centimeter simply because there are fewer square centimeters for a given number of active circuits. So what can you do? Sekar offers six strategies:
- Throw cost (decoupling capacitors, additional power and ground vias, more power I/Os, more routing area for power distribution) at the problem.
- Use CAD tools that optimize a design for power density.
- Use next-generation decoupling capacitors.
- Use integrated dc-dc converters to transform higher-voltage, lower-current supplies into lower-voltage-higher-current supplies.
- Use clock-data compensation to adjust clocks as needed for less circuit sensitivity to power-supply noise.
- Apply microarchitectural di/dt control.
You can read the full blog post here.