Friday Video: All about the TSMC ESL Reference Flow 12

ESL Reference Flow 12 is the latest generation TSMC reference flow for electronic system-level (ESL) design. The TSMC ESL Reference Flow 12 inserts power, performance, and area (PPA) indices into an ESL design flow, which  enables designers to explore meaningful PPA design-space exploration using different system architectures at a very high abstraction level. The ESL flow includes virtual platform prototyping, high-level synthesis (HLS), and ESL to RTL verification developed in collaboration with Cadence. An SoC Interconnect Fabric Flow addresses SoC timing issues arising from long on-chip interconnects. Using the TSMC ESL Reference Flow 12 helps resolve many design issues early—at the architecture level—to more quickly optimize system performance and reduce latency.

For more information, click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization, SoC Realization, System Realization, TLM and tagged . Bookmark the permalink.

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