Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)

Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, 36 12.5Gbps GTX serial transceivers, and 1200 user I/O pins. All in about 20W (!!!). The only fly in the ointment, if you want to call it that, is that no one on this planet can make this FPGA as a monolithic device. The Virtex-7 FPGA is a 2.5D assembly that combines four FPGA tiles on a silicon interposer.

Here’s an exploded diagram of the FPGA assembly:

The four active FPGA tiles are made by TSMC using its 28nm HPL (high-performance, low-power) high-K metal-gate (HKMG) process technology. TSMC also makes the silicon interposer, a massive 65nm IC in its own right, weighing in at 775 square millimeters. Although the silicon interposer for the Xilinx Virtex-7 2000T has no on-chip active elements, it still takes a multi-billion-dollar fab to make this piece of silicon. After the silicon pieces are fabricated at TSMC, Amkor provides the assembly expertise, combining the TSMC silicon with a package from IBIDEN.

For an in-depth look at the low-power design aspects of this announcement, see my blog post at www.low-powerdesign.com.

EDA360 Insider will provide a more in-depth technical analysis of the 3D aspects of this Xilinx announcement on the next weekly 3D Thursday, October 27.

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV and tagged , , , , , . Bookmark the permalink.

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