After the previous post on the announcement of the Altera SoC FPGA ran in EDA360 Insider—see “The other shoe drops: Altera introduces SoC FPGA, mates ARM Cortex-A9 dual-core processor complex with FPGA fabric”—I heard from people at Altera. They wanted me to explain some of the interconnect aspects of the planned family in more detail. In particular, Altera wants you to know more about the interconnect between the FPGA fabric and the SDRAM controller in the HDS (Hard Processor System) section of the device. (There are two ARM Cortex-A9 processors in the HDS that run at clock rates as fast as 800MHz.) After some back-and-forth discussion, Altera sent me this revised, more detailed diagram to share with you:
As you can see from this bock diagram, there are two 128-bit AMBA AXI ports running between the FGPA fabric and the HPS. The HPS controls one of these ports to direct data transactions at IP blocks implemented in the FPGA fabric and the FPGA fabric controls the other 128-bit AMBA AXI port so that IP blocks implemented in the FPGA fabric can conduct data transactions with resources in the HPS. Note: Each 128-bit port actually consists of separate 128-bit read and write ports, as the detail in the above diagram illustrates.
Not covered in the previous blog post are the four 64-bit, bidirectional ports connecting the FPGA fabric with the SDRAM controller in the HPS. Soft IP blocks implemented in the FPGA fabric control all four of these ports, which substantially contribute to the overall bandwidth potential between the FPGA array and the HPS. These ports can be configured either as ARM AMBA AXI ports or as Altera Avalon ports.
Now the Altera SoC FPGA FPGA fabric comes in two flavors: one based on the company’s 28nm Cyclone V FPGA series and the other based on the company’s 28nm Arria V FPGA fabric. For SoC FPGA family members incorporating the Arria-based Fabric, the clock rate on all of the HPS-to-FPGA ports is 245MHz, as shown in the diagram above. For SoC FPGA family members incorporating the Cyclone-based Fabric, the clock rate on all of the HPS-to-FPGA ports is 200MHz.
One of the significant features of the Altera SoC FPGA family is the availability of additional hard-core SDRAM controllers embedded in the devices’ FPGA fabric. As the above diagram shows, there can be as many as three of these controllers depending on the family member. This added memory-control capability opens up interesting possibilities for memory-intensive designs.
For more info on the Altera SoC FPGA family, click here.