Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made by the panelists, but first I thought I’d blog my panel introduction, titled “Steve’s Improbable History of 3D assembly” and patterned after an animated TV segment titled “Peabody’s Improbable History” from the old “Rocky and Bullwinkle Show” in the 1960s. In that segment, a super-genius talking dog named Mr. Peabody and his boy Sherman repeatedly traveled back in time using a time machine that Mr. Peabody had invented. The time machine was appropriately called the “Wayback.”
I do not have a Wayback machine, but I do have the next best thing. It’s called the Internet and it allows me to call up all sorts of images from the past. With these images, I can show you that 3D is hardly new. Electrical engineers have been thinking and working in the third dimension for at least six decades.
The first image I called up during my panel intro was from the year of my birth: 1953. Let me introduce you to Project Tinkertoy:
This military electronics project from 1953 attempted to bring more organization and more modularization to a world of electronics that was essentially based on point-to-point wiring—done by hand of course. Project Tinkertoy recognized that there would be a shortage of skilled soldering technicians as electronics found its way into more and more military, industrial, and consumer products. It sought to develop a modular system, a 3D system, based on rectangular ceramic wafers—each loaded with different components. Vertical wires made electrical connections between the wafers, which would then be assembled into functional modules. The modules would then be assembled into systems such as the radio altimeter shown in the lower right corner of the image above.
You might well ask, “Why didn’t they use printed circuit boards?” Not invented yet is the simple answer. Also, note the tubes (gaseous FETs). In 1953, the transistor was a mere five or six years old and still made by diffusion processes more resembling alchemy than materials science. Ditto the IC, of course. Not invented yet. These were still early days for electronics yet 3D was there.
So what of the IC? Well, the first IC was also the first 3D IC. I’ll bet you had not considered that. I had not until I created this presentation. Here’s a photo of Jack Kilby’s first IC prototype, assembled late in 1959 at Texas Instruments.
Sure looks pretty 3D to me.
Let’s now jump from 1959 to 1979. Here’s a photo of the Mostek 38P70, one of the earliest microcontrollers.
I actually used this product in a design for HP. It’s hard to miss that MK2716 EPROM riding piggyback on top of the MK38P70 microcontroller. In those days, it was hard to put the EPROM on the same die as the microcontroller. The EEPROM and logic process technologies were difficult enough to implement without intermarriage. So the approach Mostek took was to develop special 3D packaging (package on package) that allowed a standard ceramic-packaged 2Kbyte EPROM to ride piggyback on the very expensive, hand-made MK38P70 package. You only used this approach for prototyping (which I actually did do) unless you didn’t care about unit costs. It was an expensive solution.
Here’s another example of Mostek’s package-on-package approach circa 1979:
This is the Mostek MK4332D 32Kbit DRAM, which answers the question “What do you do when your process technology can only give you 16Kbit DRAMs but your customers want more memory capacity?” The answer: take two 16Kbit DRAM die in leadless ceramic packages and mount them on an 18-pin “ceramic interposer” (formerly known as a multichip or multicavity package) and then sell the device as a 32Kbit DRAM. System vendors with limited board space bought these to keep overall product size to a minimum. That’s always been one of the attractions of 3D assembly.
Staying with the DRAM theme for a moment, here’s another example of package-on-package design from 1985:
This pair of 64Kbit, plastic-packaged DRAMs in DIPs have been stacked and soldered together at the Texas Instruments factory to produce a 128Kbit device with a small footprint. This product is destined for a socket in an IBM PC/AT clone that had broken the “640K barrier” and needed more DRAM capacity in the same amount of circuit board space. What to do? Build up. Go 3D! What could be simpler than stacking two DIPS and soldering them together, especially when this approach was already a well-known, time-honored approach to board-level prototyping at the time.
Perhaps you think I’m cheating with all of these package-on-package examples. Perhaps you think they’re not “real” or “true” 3D devices. Ok, then. Here’s a 3D memory package from 1992—nearly 20 years ago.
Irvine Sensors developed this “Memory Short Stack,” a 3D assembly of memory die, for a NASA contract and then started to work with IBM on further development.
Jumping into this century, here’s a scary photo of stacked die with wire-bonded interconnect:
As an engineer, I find this photo pretty incredible. Even more so considering that this approach is commonly used in our highest-volume products: mobile telephone handsets. If the handset manufacturers will put up with this sort of assembly, then it’s clear they’ll love “true” 3D IC assembly as soon as the early bugs are worked out.
Finally, we’re getting to recent 3D history. Here’s an illustration of the recently announced Micron Hybrid Memory Cube, which appeared in the EDA360 Insider blog last August. (See “3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs”)
The Hybrid Memory Cube delivers unprecedented DRAM performance by taking advantage of multiple DRAM channels that run through the stack. This assembly exploits the fact that all SDRAM die now consist of multiple slow DRAM arrays (operating at 200 or 400MHz) that are multiplexed and funneled through a high-speed, relatively narrow interface port such as DDR3. The high connectivity of the through silicon vias (TSVs) allow the logic chip at the bottom of the Hybrid Memory Cube stack to access multiple DRAM banks simultaneously. This arrangement boosts throughput while greatly reducing the interface’s operating frequency and therefore the interface power. For these reasons, stacked memory is clearly one of the killer apps for 21st-century 3D IC assembly.
Finally, here’s a photo of the recently announced Xilinx Virtex-7 2000T FPGA that delivers two million FPGA logic elements (plus a bunch of other functions) in one package. (For more information on this product, see “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)”)
This product lays four identical 28nm FPGA tiles side to side on a silicon interposer that’s installed in a BGA package. The 3D packaging approach allows Xilinx to offer a much larger capacity in an FPGA than a monolithic IC approach. According to the company, 3D assembly allows Xilinx to jump a generation—to go “More than Moore.” Just like the MK4332D 32Kbit and the stacked-DIP 128Kbit DRAMs discussed above did more than 25 years ago. And like the Mostek 38P70 discussed above, you can bet this FPGA is a tremendously expensive product but its immense value for high-performance prototyping overcomes the cost. This FPGA could well be used for production for some very expensive, limited-volume systems.
So as you can see, electrical engineers have been exploring the possibilities of 3D assembly for at least six decades. It’s not an idea whose time has come. It’s an idea that has continued to help deliver some of the most advanced semiconductor products in the industry for more than half a century. Today’s efforts in 3D IC design and manufacture are a continuation of that history—which is not at all improbable.