3D Thursday: How do you get to 3D ICs? The EDA view

My second panelist to speak on last week’s 3D IC panel at the 9th International SoC Conference in Newport Beach was Samta Bonsal who manages Silicon Realization Strategic Marketing at Cadence Design Systems. Samta has two hats at Cadence. One says “3D IC” and the other says “20nm.” Talk about living on the cutting edge.

Samta had two major points in her talk on the panel. The first point that I want to discuss involves the steps Samta listed for getting 3D IC assembly into mainstream manufacturing. There are three major steps according to Samta:

  1. Improve costs and yields. Look for volume success in the memory market to make this happen.
  2. Create a Performance/Power/Price advantage. No electronics company can resist the allure of a triple advantage in all three of these metrics. Look for consumer applications, particularly mobile phone handsets, to lead this step.
  3. Ecosystem collaboration with a fusion of standards and business models. Look for the creation of virtual IDMs?

Samta’s second major point was that EDA is heavily involved in all aspects of 3D IC development and that Cadence already has added significant features to its tools over the past three years to permit 3D IC development using the OpenAccess database as a backbone for this work. The first production tapeout of such as design was in 2010. Here’s a graphical view of 3D coverage in the Cadence IC flow:


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, Ecosystem, EDA360, Silicon Realization, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

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