Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: How do you get to 3D ICs? The EDA view”) This week, I wanted to write up some of the other panelist talks.
My last panelist, Zvi Or-Bach, is President and CEO at MonolithIC 3D, is a serial semiconductor entrepreneur. He’s not content with the benefits of 2.5D and 3D assembly. His company is shooting for true 3D IC manufacturing. In his talk, Or-Bach pointed out that all semiconductor memory vendors are going 3D. In particular, the Flash EPROM vendors are all looking to 3D structures to boost memory capacity. (For example, see “3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron”) “Over the next 20 years,” predicted Or-Bach, “Moore’s Law’s emphasis will switch from scaling to true 3D.”
Why? The following image tells the tale from Or-Bach’s perspective:
True 3D IC manufacturing increases the density of inter-layer interconnectivity by 10,000x relative to the TSVs used for 2.5D and 3D assembly. At what cost? The last line in the above graphic is telling: instead of a wafer-to-wafer alignment spec of 1 micron, true 3D IC manufacturing needs the precision to be on the order of 1nm. That indeed is a tall order.
Note: After publishing this blog, I heard from Deepak Sekar who is the Chief Scientist at Monolithic 3D. He wanted to clarify the table that Or-Bach presented at the conference:
“Wanted to clarify one thing. What Zvi meant with this table was, ‘If you employ monolithic 3D you have lithographic alignment, which has alignment tolerance as low as 5nm (i.e. in the order of nanometers instead of microns).’ But alignment tolerance in the nm range is not a requirement for monolithic 3D. Even if your misalignment is in the range of 10nm, you can still get via sizes as low as 100nm, which is ok for monolithic 3D.”