3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: How do you get to 3D ICs? The EDA view”) This week, I wanted to write up some of the other panelist talks.

My third 3D panel speaker was Xilinx Fellow Steve Trimberger, who spoke about the Xilinx Virtex-7 2000T, a 2-Mgate FPGA built from four FPGA semiconductor tiles assembled with 2.5D technology onto a 65nm silicon interposer. (For more information about the Xilinx Virtex-7 2000T, see “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W” and “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)”)

Xilinx did not set out to develop 2.5D assembly technology for the Virtex-7 2000T, said Trimberger. The company first looked into using “true” 3D technology. But it found that it could not reliably make FPGAs using full 3D technology yet. In a lab setting, yes it was possible. But not in quantity and with the desired reliability. However, 2.5D assembly was possible now with the right amount of development.

Then Trimberger said something that I think is truly important to understand about 2.5D assembly. “The real power in multichip packaging is integrating dissimilar die.” That’s not what the Xilinx Virtex-7 2000T represents because it places four identical FPGA tiles on a silicon interposer. However, Trimberger showed this image to demonstrate where Xilinx might go:

The above image shows a different iteration of the Xilinx Virtex-7 2000T 2.5D technology where one of the four FPGA tiles has been removed and two high-performance 28Gbps SerDes die have been added. Xilinx already has discussed its 28Gbps SerDes design. In fact, the company has published a White Paper about that design. Combining the 28Gbps SerDes chips the company has already made to the Virtex-7 FGPA tiles it has already made in one product is now a matter of redesigning the interconnect pattern on the 2.5D passive silicon interposer. How long do you think that might take? This example shows the versatility of 2.5D assembly and underscores Trimberger’s assertion that “The real power in multichip packaging is integrating dissimilar die.”

Can Xilinx go even further? Sure. I’ll leave you with this slide from Trimberger’s talk:

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About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV and tagged , , , , . Bookmark the permalink.

2 Responses to 3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

  1. Roger Larsson says:

    FPGA and Memory gives very interesting possibilities.
    Memory connected with wide high speed busses…
    Perfect for image processing!

  2. sleibson2 says:

    Wide-memory connections to processing resources are great for a lot of things including image-processing, graphics, video and video editing, and for SoCs where a lot of processors direct traffic to and from main memory.

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