3D Thursday: Who is responsible for successful 2.5D and 3D assembly? eSilicon is perhaps saying “Us”

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: How do you get to 3D ICs? The EDA view”) This week, I wanted to write up some of the other panelist talks.

My fourth panelist was Paul Hollingworth, VP of Strategic Marketing at eSilicon. We did not plan it this way, but Hollingworth’s presentation was a perfect follow-on to the one from Steve Trimberger from Xilinx (see my previous blog post) because of this image, which portrays eSilicon’s MoZAIC (Modular Z-Axis IC) concept:

The image shows several 2D silicon die and a 3D IC that looks a lot like the Micron Hybrid Memory Cube (see “3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs”) all mounted to a silicon interposer.

Now eSilicon is an interesting company to be proposing this idea because it is a “value-chain producer.” In other words, eSilicon will “manage your design through production so you can focus on R&D for your next innovation.” (From the home page of the eSilicon Web site.) A company like eSilicon shoulders the responsibility for what happens when you assemble a bunch of bare die and the assembly doesn’t work. That’s been one of the major questions surrounding 2.5D and 3D development. With Hollingworth’s talk and the company’s MoZAIC concept, eSilicon is apparently saying it is willing to step up and take on this role.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , . Bookmark the permalink.

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