Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0

Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open SystemC Initiative) TLM 2.0 interfaces into the game. These interfaces define how TLM models communicate and standardization of these interfaces within IEEE 1666 will improve model interoperability and will encourage model reuse at high abstraction levels. All of this technology forms a critical infrastructure for virtual prototyping—an essential part of future System and SoC Realization efforts.

The EDA industry often gets criticism for not cooperatively creating standards that benefit the wider electronics industry. This is not one of those times. The P1666 SystemC Working Group includes representatives from Accellera, Cadence, Freescale, Intel, JEITA, Mentor, NXP, OSCI, ST Microelectronics, STARC, Synopsys, and Texas Instruments. We owe all of the Working Group members a note of thanks for this successful effort. It’s an extremely important advance in system- and SoC-level design and modeling.

Further, I think you’ll need a pretty jaundiced outlook to think that this new standard isn’t getting pretty wide industry support. I’m certain that people with such an outlook are out there and we may be hearing from them. Meanwhile, for not-so-jaundiced perspectives on this development, see Richard Goering’s blog post and Brian Bailey’s blog post on the topic.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM and tagged , , , , , , . Bookmark the permalink.

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