Who else wants to overcome power-related IR-drop and electromigration challenges in mixed-signal ASIC designs?

How many times have you discovered unanticipated IR drop or electromigration problems in the power grids of your complex analog or mixed-signal ASIC? How easy was it to fix these problems? Virtually all modern IC and SoC designs include mixed signal elements. Most of these systems must connect millions of gates, DSPs, memories, and processors to the real world through one or more analog or mixed-signal I/O subsystems such as a display, an antenna, a sensor, a cable, or an RF interface. Successfully taping out a mixed-signal design on schedule with the lowest power consumption and within budget is becoming more and more challenging.

Please join us for a free one-hour webcast that looks at ways to meet these challenges effectively and efficiently. This one hour webinar session covers topics including:

  • Comprehensive SoC power-integrity analysis and design for multiple mixed-signal ASIC design styles
  • Performing “what-if” power-rail analysis in the early stages of design to avoid last-minute surprises
  • Advanced IR-drop/electromigration verification techniques to ensure long-term power integrity
  • Automated power-network optimization that mitigates manufacturing and variability issues

Sign up today!  Register here. It’s free.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Silicon Realization and tagged , , , , . Bookmark the permalink.

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