I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)” and “Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells, consumes only 20W”) Now Deepak Sekur, Chief Scientist at Monolithic 3D, has written his own blog titled “Is the Buzz around Xilinx’s 2.5D FPGA Justified”. This notion of buzz and buzz worthiness doesn’t really work all that well for me in the engineering world. Packaging issues and 2.5D/3D technologies aren’t popularity contests the way mobile phone handsets and cars are. Further, I don’t typically think of engineers as particularly “buzzy” creatures. It’s more a term of endearment used by marketing cats who can’t talk tech with authority, and that definitely doesn’t describe Sekar. He’s as technical as they come and his blog on this topic is also technical so I can recommend it to you despite the title.
In his blog entry, Sekar explains “Why Silicon Interposers?” (thermal coefficient of expansion, high-connectivity microbump pitch, and no need for underfill), “Implications and Future Prospects” (lower NRE costs than equivalent ASIC designs and the ability to combine die from different IC processes), and “Cost” implications (current silicon interposer wafers cost $10,000 ?????).
Mysteries to be discussed. Take a look. Join the buzz.