There’s just too much 3D happening this week to confine it to this Thursday so I’ll be writing about 3D topics all this week. Last Friday, I attended a 3D workshop sponsored by the Irvine chapter of the IEEE CPMT (Components, Packaging and Manufacturing Technology) Society. There were more than 150 attendees packed into the Jazz Semiconductor auditorium in Newport Beach and I thought it was an excellent event. The keynote speaker, Muhannad Bakir who is an Associate Professor at Georgia Tech’s School of Electrical and Computer Engineering, did an excellent job of explaining what’s causing 3D packaging technology’s momentum to accelerate. The first thing Bakir presented was this graph:
This image graphically depicts the end of Dennard scaling at 90nm. Put another way, this graph shows the end of clock scaling. Three to four decades of semiconductor design practice now obsolete. Clock scaling is no longer the path to ever-improving system performance. This ought not to be news to you.
So what are we doing about it? Well multicore design is the new clock scaling. If we can’t make one core go faster (actually we can, it’s just a lot harder than it used to be), we can at least use that bounty of transistors conferred upon us by Moore’s Law to replicate cores and boost system performance through parallelism.
Perhaps you’ve heard. There’s no free lunch. This next graph from Bakir’s presentation introduces you to the memory wall:
As the number of on-chip processor cores increases, you get more system performance assuming you can keep the processor cores fed with instructions and data. Eventually, you can’t. That’s when your system design has hit the memory wall.
Now the memory wall is an artifact caused by several factors. One factor is the speed of the memory cells in your memory array. You can get more effective speed by banking memory arrays and connecting to these banked arrays with a high-speed memory interface. That’s what we do with DDR DRAM and that’s an effective strategy for combating the memory wall, to a point. But as bandwidth needs become greater, memory banking gets deeper and latencies stretch to the point where processors must wait hundreds of clock cycles to get the data they request from the DRAM.
The result, as amply covered in this blog and elsewhere is to use more memory in parallel and the best way to do that is with 3D memory stacking and Wide I/O memory access. This is one of the two major drivers for 3D packaging said Bakir.
So what are the consequences of taking this 3D path to system design? Well, one such consequence is heat. Lots of heat. When you make things a lot more compact but aloow them to dissipate about the same amount of power, they get hotter. So one of the things Bakir is working on is liquid cooling of 3D chip stacks using microfluidic channels formed in the silicon. Here’s a photo:
However, it turns out that digging tunnels through the silicon may not be the most efficient way to cool a 3D IC stack. Bakir showed this example of the formation of micropin heatsink fins on the silicon.
It turns out that these structures, which resemble macroscale aluminum heat sink pins, are very effective for a liquid-cooling approach.
And then there’s the topic of inter-die interconnect and the second major application for 3D packaging: incorporating sensors into system design. In particular, Bakir is interested in biosensors, disposable biosensors, and creating a way to easily connect and disconnect such sensors from 3D systems. Here’s the image of a reusable connection scheme Bakir showed in his talk:
These are spring connectors formed on the top of a chip. They’re nanoscale spring connectors that represent a reusable interconnect scheme that allows you to pop a disposable biosensor on top of an electronics module, run a test, and then discard the sensors. The electronics package is therefore reusable. Think of it like the test strips used wtih glucometers. Same idea. Much smaller scale.
And this was just the keynote.