3D Week: The three interconnect crises of the electronics industry and the inevitability of 3D. Believable?

Many people in the electronics industry view 3D IC assembly as not being in the mainstream. That’s easy to understand. It’s not at the moment. Yet I do believe in the inevitability of 3D assembly. Here’s why.
At last week’s IEEE 3D workshop in Newport Beach, Professor Muhanned Bakir of Georgia Tech concluded his morning keynote speech by noting that the industry has gone through three interconnect crises in the last 60 years. The first such crisis occurred during the mid 1950s. Bakir called this crisis the “tyranny of numbers.” During that era, electronic system designs became large enough that the interconnect technology of the day, point-to-point hand wiring, became completely unusable. According to Bakir, this crisis need gave birth to the IC itself and that’s true. It also gave birth to the printed circuit board. Looked at from one perspective, both the IC and the pc board were interconnect solutions to component-integration problems caused by a failure of the era’s manually built interconnect technology to keep pace with system complexity. Think about wiring today’s 256-bit buses by hand and it’s laughable today, isn’t it? That’s all there was in the 1950s.

According to Bakir, the second interconnect crisis occurred in the mid 1990s when on-chip wire length became so long that the increasingly resistive wires started to introduce significant circuit delays in signal timing. At first, IC designers increased gate output drive strengths in an attempt to fight the problem. But this too was an interconnect problem and the effective answer was to replace aluminum with copper on-chip interconnect, as many as ten (or eleven!) wiring layers, an emphasis on short-wire architectural design, and repeaters for long wires where short wires simply couldn’t be employed.

And now we are deep into the third crisis, which is often characterized by walls. There’s the memory wall, caused by an inability of chip-to-chip interconnects to deliver the bandwidth needed by multicore chips. And why are we using multiple processor cores? Because of the power wall. Simply cranking clock rates to get performance ran us straight into the power wall and processor clock rates are no longer climbing nearly as fast as they once did to prevent chips from melting from the resulting increase in heat density.

What’s the solution to this third interconnect crisis? Bakir believes, as do I, that the solution to this crisis is 2.5D and 3D assembly. These packaging technologies permit far more interconnect density and allow drive strength to fall because the I/O drivers no longer need to wiggle wire bonds and pc board traces. For this reason, I believe 3D assembly is inevitable.

What about you?

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization and tagged , , , . Bookmark the permalink.

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