3D Week: Driven by economics, it’s now one minute to 3D

At last week’s IEEE 3D Workshop held by the local CPMT (Components, Packaging, and Manufacturing Technology) chapter, Dr Philip Garrou gave a presentation where he talked about the favorable economics of 3D and how those economics are now driving 3D IC assembly’s adoption. The first thing to understand, said Garrou, is that it’s no longer business as usual in the IC business. Dennard scaling (faster, lower power) is dead and has been dead for perhaps the last four process nodes. Strained silicon and high-K metal gates postponed the inevitable, but the inevitable did finally arrive. To get further reductions in package size and system power consumption and to get substantial boosts in system bandwidth, there’s only one path forward: 3D IC assembly.

According to the data gleaned from presentations by Samsung, Toshiba, AMD, and others, 3D IC assembly gives you the equivalent performance boost of 2 IC generations (assuming Dennard scaling wasn’t dead). Garrou then quoted AMD’s CTO Byran Black, who spoke at the Global Interposer Technology 2011 Workshop last month. AMD has been working on 3D IC assembly for more than five years but has intentionally not been talking about it. AMD’s 22nm Southbridge chips will probably be the last ones to be “impacted by scaling” said Black. AMD’s future belongs to partitioning of functions among chips that are process-optimized for the function (CPU, Cache, DRAM, GPU, analog, SSD) and then assembled as 3D or 2.5D stacks.

There’s another way to look at the economics of 3D, said Garrou. He then proceeded to put up a chart of IC vendors and their 2009 revenues. Only the top 18 semiconductor vendors had revenues in excess of $3 billion/year. The rest clearly could not possibly purchase the equipment and fabs needed to continue Moore’s-Law scaling. Only the most elite of semiconductor vendors will have enough cash to proceed further down the scaling path. Perhaps three logic IDMs, three foundries, and three to five memory vendors will establish 22nm fabs.

Will the rest go under? Hardly. As AMD’s Black said, the industry “will stagnate if we don’t get 3D.” Semiconductor scaling may have been the main path to advancement in the past, but innovative die-level assembly techniques with partitioning along functional levels (see Byran Black’s statements above) permit a new flowering of system-level semiconductor innovation.

As long as Dennard scaling worked, it made sense to incorporate everything possible on one chip. However, even then, it was hard to justify mixing logic with DRAM, for example, because DRAM processes typically cost less per square mm by getting by with three or four metal layers instead of the ten or eleven metal layers needed by advanced logic SoCs. Similarly, analog circuits don’t do as well with nanometer geometries and RF circuits, well they’re and entirely different sort of animal.

Before 2.5D and 3D assembly took off, multi-die assemblies relied on multichip module packaging and wire bonding. These were not cost-effective in many cases. Microbumps and the rapid improvement in TSV (through silicon via) manufacture have changed the economics of multi-die assembly. As a result, said Garrou, many vendor roadmaps show 3D and 2.5D assemblies being introduced now through 2013.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization. Bookmark the permalink.

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