3D Week: The State of 3D IC assembly—December 2011

The nascent 3D IC industry’s foremost scribe, Francoise von Trapp, has just published a wrap up of this weeks 3D IC assembly conference held by the Research Triangle Institute in Burlingame, California. She notes some of the real highlights, which I’ll quote here from her blog post:

“Here’s where everyone seems to agree – 3D is the way to solve future scaling issues. When we say ‘3D is here’ what we really mean, is ‘The NEED for 3D is here.’”

“Douglas Chen-Hua Yu, from TSMC said that with all the debate and argument surrounding 3D, you can’t argue that there is a paradigm shift from device scaling to system scaling, and that the industry has been re-defined by mobile computing.”

“Altera’s Bradley Howe predicted that there are 8-10 years left to scaling, and then 3D will be the solution.”

“LeiLei Zhang, of graphic chip maker NVIDIA, was even more direct in her comments. ‘Scaling is ending. Let’s get over it (EUV) and move resources elsewhere.’”  3D perhaps?

“There is work left to be done.”

Well, yes, there’s always work left to be done, isn’t there? Otherwise, the engineers lose interest, pick up their toys, and find another sandbox. However, there’s really no controversy left in the 3D IC proposition. It’s the way to get the badly needed, system-level connectivity while taking advantage of multiple IC fabrication processes individually optimized for logic, memory, analog, and RF functions. It’s the way to take advantage of the performance gains multicore processing offers without hitting the memory wall. It’s the way to continue down the path of system-level miniaturization. It’s the way to avoid using a crazy quilt made from thousands of multilevel wire bonds with the consequential costs and parasitic impedances we really don’t want.

It’s the crystal-clear way to the future.

Naysayers need to step into the Wayback machine and take a quick trip back to the late 1980s. Sample the ambiance of those times including the “controversy” around surface-mount technology (SMT). Dedicated through-hole advocates saw many problems with SMT:

“You can’t probe it,” they said. Enter JTAG.

“No one will spend the extra money for JTAG circuitry on chip,” they said. Enthusiastic application of Moore’s Law over more than two decades killed that objection deader than a cracked vacuum tube.

“Not enough components are available in SMT format,” they said. Again time fixes much and patches over the rest.

“You can’t apply components to the circuit boards by hand,” they said. True. Legions of pick-and-place robots supplanted the mind-numbing repetition of the through-hole push line.

SMT brought in the era of the SOIC, the BGA, and the leadless carrier. There’s still work to be done with SMT. We use it anyway. Without blinking. Not true 20 years ago. 3D IC assembly today is where SMT was 25 years ago.

For me, the most striking indicator of where we are with 3D IC assembly at the RTI 3D conference was Doug Chen-Hua Yu telling the audience that TSMC was ready to be the industry’s one-stop IC foundry—AND—3D IC assembly house. When TSMC says it wants in, there’s something big in there.

So we end 2011 poised for great things. See you in 2012.

To read Francoise von Trapp’s full 3D essay, click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization. Bookmark the permalink.

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