The Santa Clara Valley (SCV) Chapter of the IEEE Solid State Circuits Society is hosting a 3-hour short course in low-power design a the end of this month. The course is divided into two parts:
- Fundamentals of low-power design and a review of well-established low-power design techniques
- New low-power design techniques that will come into their own based on current technology and application trends.
This is a rare opportunity to get a concentrated presentation from Professor Jan Rabaey of UC Berkeley, who happens to be an excellent and engaging speaker. The short course will be taught at the TI Silicon Valley Auditorium (formerly National Semiconductor), 2900 Semiconductor Drive, Santa Clara, CA.
The charge is $50 plus a $3.74 event fee. Register here.