Registration for CDN Live—the 2-day technical conference for Cadence users being held on March 13 and 14 in San Jose—has just gone <er> live. Before I give you the link, I wanted to let you know about some of the papers being presented because they vary widely and should interest anyone involved in the nitty gritty of chip design.
There are eight parallel tracks at the event this year:
- Digital IC Design
- Mixed Signal/Low Power Design
- Custom IC Design
- IC Verification
- SoC Design and Design IP
- System Design and Software Development/Integration
- System Verification
- High-Performance Design
There will be presentations on leading/bleeding-edge design at the 40nm, 28nm, 20nm, and 14nm nodes, several papers on low-power design approaches, discussions of accelerated development using high abstractions levels and system-level simulation, and some designer experiences with design IP. In all, there are 40 presentations queued up for the first day and 52 presentations for the second day, 92 presentations in all.
Click here for more info.
EDA360 Insider 
SKILL programmers should take note of CUS006, “Creating an xUnit Skill Test Harness” by Sze Tom of AMD. The original developer was Tara Clark.
This brings to SKILL one of the prerequisites for a modern programming language: a unit test framework.