3D Thursday: Count Renesas in with the 3D IC poker game, says Nikkei Electronics

Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the lines, it’s the just-ratified JEDEC Wide I/O standard and the resulting Wide I/O DRAMs that’s pulling Renesas into the fray. The target—no surprises here—is mobile phone ICs.

For more information on Wide I/O SDRAMs, see:

Cadence Releases Industry’s First Wide I/O Memory Controller IP Solution

3D Week: JEDEC Wide I/O Memory spec cleared for use

Wide I/O. Don’t leave your SoC without it

3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?

3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O and tagged , , , , . Bookmark the permalink.

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