3D Thursday: Gabe Moretti nails 3D IC—economics, architecture, and testability

Gabe Moretti is a long-time EDA analyst and commentator. His latest “Assembling the Future” newsletter highlights and summarizes key economic, architectural, and test issues associated with 3D IC assembly. Gabe writes:

“Given the semiconductor manufacturing environment the industry has grown accustomed to, the difficulties of 3D architecture would make one quite conservative in predicting a high ramp for this method. But, semiconductor manufacturing is about to become quite different from the past. The move from 28 nm (or even 22 nm) process to 20 nm and below is proving to be a discontinuity point in our industry. We have reached a limit in the way we can bend light. We are knocking at the front door of X rays (10 nm) without really knowing what we will do when the door is open.”

Gabe then resorts to a Star Trek analogy (always a winner with me) to highlight the key architectural issue with 3D design:

“To a design engineer accustomed to thinking in 2D, architecting a 3D system will be a challenge. As Admiral Kirk says in The Wrath of Khan, one must be trained to think in 3D, and Khan, to his misfortune, was not.”

This single sentence on testing and testability is perhaps the best summary I’ve seen on the topic:

“Since testing of TSV can only be done in-package the system must provide hierarchical ATPG for testing logic-to-logic interconnect as well as BIST for testing memory-to-logic interconnect.”

As is Gabe’s conclusion:

“Development and manufacturing costs at 20 nm and below are so high that a significant portion of potential products become financially unfeasible. A 3D solution with dies that spans the 90 to 32 nm processes can provide a viable solution and offer consumers a plethora of gadgets at attractive prices.”

Go read the entire article in the newsletter.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization. Bookmark the permalink.

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