How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister

Trying to suss out the differences among virtual prototyping, emulation, and FPGA prototyping? Richard Goering recently interviewed Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, in Goering’s Industry Insights blog and the interview covers a range of system-level design topics. Here’s what Frank had to say about the various approaches to prototyping:

“As I wrote in a recent EE Times article, you need prototyping throughout the flow at different stages. With virtual prototypes you get good speed for software debugging, but you don’t get the accuracy you need for hardware verification. So you first bring in RTL simulation, which is in a sense a prototype, but it doesn’t execute software very well. That’s when you bring in emulation. Now higher-speed software development and execution become feasible, you have better debug on the software side, and you still have good debug insight into hardware.

But at some point that is still too slow as well, so you may want to bring in an FPGA-based prototype where you have even more speed. But what you have to take into account for FPGA-based prototypes is that every change you make on the hardware side takes longer. So you want to use it at a more stable phase of the RTL. At Cadence, we provide technology that allows you to reuse what you’ve done in the Palladium emulator to make the FPGA-based prototype bring-up easier.”

See the full interview here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at
This entry was posted in EDA360, System Realization, Virtual Prototyping and tagged , . Bookmark the permalink.

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