3D Thursday: CEA-Leti launches Open 3D IC assembly partnership program

ElectroIQ reports that CEA-Leti in Grenoble has just launched an Open 3D IC program to permit companies more open access to the 3D IC assembly technologies developed at the research center. Last December, CEA-Leti and ST-Ericsson made a joint presentation about a very advanced 3D IC SoC and memory project that employed Wide I/O SDRAMS (see “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?”).

With this new announcement, CEA-Leti appears to be making that extremely advanced technology more accessible. There are actually several 3D IC technologies included in the program:

  • 3D design and layout including a design rules manual (DRM) and 3D design kit
  • Layout capabilities based on Cadence Virtuoso with many 3D enhancements
  • Through silicon via (TSV) design and fabrication technology
  • Backside redistribution layer (RDL) design and fabrication technology
  • Microbump, micro pillar, and under bump metallurgy (UBM)
  • 3D test methodology and technology

For more information on the CEA-Leti Open 3D program, click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O and tagged , , , , , , . Bookmark the permalink.

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