3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say ‘Tour de Force’?”) Now, Eric Beyne, Director of Advanced Packaging and Interconnect Research at Imec has published an article with key lessons learned from related work associated with stacking a special 3D logic die with TSVs (through silicon vias) and microbumps on a DRAM die and it’s a worthwhile read.

Briefly, the key lessons are:

  • You need a minimum die thickness of 50µm to handle local hot spots on the logic die. Otherwise the stacked DRAM die may receive too much heat from the logic die, which will degrade the DRAM’s storage-retention time.
  • Experiments with the WIOMING design led to the creation of more than 40 new 3D-specific design rules and models.
  • You will need clear agreements supply chain partners on a variety of parameters including ownership, liability, and value distribution for all 3D IC assemblies.
  • Currently, the effort and expense involved with 3D design mandate a clear and convincing target application.

Partners involved in this work with Imec include: Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, Qualcomm, Xilinx, Altera, and Nvidia.

Read the full article on the Semiconductor Packaging News Web site here.

Note: EDA360 Insider covered this development last year. See “3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
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