Power-intent methodologies: Can’t we all just get along?

All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the past five years, there have been two formats for expressing power intent: the IEEE’s Unified Power Format (UPF) and Si2’s Common Power Format (CPF). Efforts are under way to develop a converged methodology for power-intent descriptions. The latest statement of that work just appeared on the EETimes Web site, in an article titled “Power Intent Formats: Light at the End of the Tunnel?” In this article, authors from Qualcomme, Cadence, ARM, and TI describe some of the most important differences between the two methodologies and the ongoing efforts to create one industry standard methodology using the best features of both existing methodologies.

Every designer involved with SoC and Silicon Realization efforts should already have a clear idea as to why descriptions of power intent are important. Almost all designs at 45nm and below use one or more power-reducing design techniques including multiple Vt transistors, multiple supply voltages, and dynamic voltage and frequency scaling. The addition of power gating to facilitate some of these methods introduces design challenges that must be addressed. As the article states:

“These advanced techniques cause a huge increase in complexity of both design and verification. They introduce many different power states, usually under software control. There are protocols that must be followed to successfully switch various parts of the design between power states, and have them switched off and brought back up when required without error. In addition to the functional design and verification needs this implies, there are many other needs we refer to as structural needs. Each power domain needs to be fully separated from other power domains, using appropriate isolators or level shifters on every signal that crosses the domains. These advanced techniques drove the need to express specifications and rules, requiring a set of design semantics not envisioned or supported by hardware description languages, which previously abstracted away power and ground connections during logic design phases as unnecessary facets of physical implementation.”

The article concludes “Significant progress is underway toward methodology convergence. After five long years, we finally can see the light at the end of the tunnel. And for once it’s not an oncoming train.” If you want a deeper view into the details of these efforts, take a look at the article.


About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization and tagged , , , , , , . Bookmark the permalink.

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s