A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the purchase price of an end product (such as a mobile phone or a tablet) that pairs Wide I/O SDRAM with a logic chip using 3D assembly techniques. Greenberg challenged me to check his math. I’m going to do just that in this blog post. See what you think.
We need to start with the incremental cost of adding TSVs (through silicon vias) to a multiprocessor SoC (MPSOC). To do that, we need to figure out much added cost there would be to add TSVs to an MPSoC die.
Well, how big is an SoC or MPSoC die that might use a Wide I/O SDRAM?
Without naming names, let’s look at a series of such SoCs from one vendor. This SoC family includes single- and multi-processor designs built with 65nm and 45nm process technology. Die sizes range from 40 to 110 mm2. Marc then conjectures that a “representative” applications processor SoC measures 9x9mm, giving an area of 81mm2. That’s right in the middle of the range for the existing application processor family described above.
You can fit approximately 800 such die on a 300mm wafer. (Marc provided a handy reference pointer for this computation.) Let’s suppose we get about 70% yield from this wafer (or pick your own yield number), resulting in 560 known good die per 300mm wafer.
Now all we need to do is figure out the incremental cost per wafer for adding the TSVs. Here, the numbers are all over the map. At the recent 3D Architectures for Semiconductor Integration and Packaging event held in Burlingame, California, I heard incremental cost numbers as high as $800 per wafer for adding TSVs. I’ve also read estimates of $150 (click here) and seen an estimate that the ultimate cost will be about $25 (click here) once we get the process nailed down.
What number should we use?
Let’s pick something between $150 and $800 that doesn’t require too much “hard” math. How about $560? That would make the incremental cost of adding TSVs to an SoC work out to exactly $1 per known good die. You can’t get much easier than that. If you prefer the $150 number, then it’s 27 cents per die. If you believe that eventually it will cost $25 per wafer to add TSVs, then the incremental cost is 4.5 cents per die.
In the end, you’ll see it doesn’t really matter which of those three per-die incremental costs you pick. You win in any case.
Why? Because, as Marc has been known to say, the power savings you get from using Wide I/O SDRAM permit you to shrink the battery powering the end product. You can save $1 to $3 in the battery alone from those power savings, not to mention the board-cost savings derived from reducing the IC real estate footprint when the SDRAM disappears from the board and climbs on top of the application processor.
Now, before you get all technical on me, let me acknowledge that there are a host of factors not included in this SWAG cost analysis. Neither Marc nor I compared the relative cost of compression bonding the Wide I/O SDRAM to the SoC versus wire bonding. We did not include the cost savings of entirely eliminating the packaging for the Wide I/O SDRAM nor the incremental cost of the more complex encapsulation for the 3D stack. Also, we did not factor in the cost savings resulting from the elimination of some 120 fewer pins on the SoC, which no longer needs an external SDRAM interface, and we also did not factor in the yield loss due to stack assembly.
So, is this a back-of-the-envelope calculation? You betcha! Is it a good engineering estimate for making a decision to look more seriously into 3D integration. I’d say so.
By the way, Cadence offers a Wide I/O SDRAM controller and PHY IP plus an appropriate memory model for your SoC verification efforts, just in case you feel the sudden, urgent need to design an SoC with TSVs to pair with a Wide I/O SDRAM. Feel free to check them out.