The value of IP Subsystems for ASIC and SoC Realization teams—Richard Goering interviews ChipEstimate’s Adam Traidman

Richard Goering recently interviewed the founder of ChipEstimate.com, Adam Traidman, in his Industry Insights blog and covered a range of IP topics. I found Adam’s take on IP Subsystems particularly interesting:

“In my mind an IP subsystem is a set of smaller components that together represent a higher level of value. There is a trend towards subsystems because, as the industry matures, designers will find value in larger building blocks. Our building blocks have evolved up through several levels of abstraction. Instead of customers coming to us and asking for the individual PLLs and DLLs and I/Os, they now come to us and say “we’d like a completely verified digital and analog DDR4 solution that’s pre-tested and perhaps even laid out in a specific process technology.”

Coincidentally, the Semico IMPACT IP conference is coming up in May and there will be a focus on IP Subsystems. For more information on the IMPACT IP Conference, click here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in EDA360, IP, SoC, SoC Realization, System Realization and tagged , , , , . Bookmark the permalink.

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