3D Thursday: Three on 3D—papers from ISSCC

San Francisco Tech writer Rik Myslewski just published a long article on the UK’s “The Register” Web site covering three 3D papers given at last week’s ISSCC. The papers were presented by IBM (“3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias”), the University of Michigan (“Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores), and the Georgia Institute of Technology (“3D-MAPS: 3D massively parallel processor with stacked memory”).

The IBM paper describes an experiment to attach a cache memory chip (or die stack) to a “processor-like” chip or proxy (not an actual processor, apparently). The experiment seeks a way to provide more L3 cache memory to IBM’s Power7 multicore server processor chips in a way that permits the L3 cache to operate at high speeds (2 GHz) even with a 4-die stack.

The University of Michigan’s Centip3De processor operates slowly (as slow as 10MHz) at near-threshold power supply voltages to keep power consumption low.  The idea is to surround these slow processors with gobs of memory (cache and DRAM) using 3D IC assembly techniques.

The Georgia Institute of Technology’s paper also deals with massively parallel computing and the work resulted in an operable system. The design implements 64 VLIW processor cores running at 277 MHz. Each core is connected to a 4Kbyte SRAM cache using through-silicon vias (TSVs) and 3D IC assembly techniques.

You can check out Myslewski’s full article here.

About sleibson2

EDA360 Evangelist and Marketing Director at Cadence Design Systems (blog at https://eda360insider.wordpress.com/)
This entry was posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization and tagged , , , , , . Bookmark the permalink.

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